Semiconductor components, such as components for optoelectronic applications, frequently use layered heterostructures of semiconductor materials (e.g. PIN junction or multi-quantum wells) where semiconductor devices are mostly built from layer upon layer in the vertical direction on a substrate. The layers are selectively deposited and selectively removed using various deposition and material removing processes. These layers can be on the order of nanometers to micrometers in thickness. The methods are used to create microelectronic semiconductor devices, such as diodes and transistors, on the substrate.
Device processing takes primarily one of two technologies. One technology incorporates a process wherein the substrate goes through a variety of masking and etching steps. The second technology incorporates a process known as epitaxy wherein the semiconductor devices are grown atomic layer by atomic layer by a process such as chemical vapor deposition. Either technology singularly, or in combination, can be used to build complex integrated devices having three-dimensional structures.
In the course of fabrication, whether the discrete devices are formed by epitaxy or mask/etch, some processing steps leave an exposed device side wall. These side walls form conductive oxide layers in some material systems, such as, but not limited to, InP and InGaAsP. The side wall is subsequently passivated so that no leakage current will exist between individual material layers forming the semiconductor device, and/or between the layer above to the layer below the semiconductor device. Commonly, passivation is achieved by the application of a passivation material, such as, but not limited to, BCB polymer and PMMA photoresist, that is spun around and over the device to encapsulate the side wall.
After the passivation layer is formed, the surface of the passivation layer is planarized with the top of the device. Planarizing is required, for example, such that a high definition metallization layer may be formed across the surface to effect electrical interconnection with other devices or components.
One method of planarization is by use of a chemical etching process that etches the surface of the passivation layer to a level flush with the top surface of the device; a process known as etch-back. Planarization using a chemical etching process is not without complications. FIG. 16A is a cross-sectional view showing a conforming passivation layer 86 encasing a multi-layer semiconductor device 82. The passivation layer 86 conforms to the device side wall 83. FIG. 16B is a cross-sectional view showing the passivation layer 86 after an etching process was used to lower the passivation layer surface 89 to substantially flush with the device surface 87.
A common problem with the etching of a surface containing two materials is known as trenching. Trenching is found at the interface of the two materials where enhanced etching can occur. The enhanced etching at the material interface forms a trench 88, as shown in FIG. 16B. The trench 88 can extend from the passivation layer surface 89 to the next material layer or to the substrate 80 adjacent the device side wall 83. This trenching can, in some cases, allow the exposed device side wall 83 to form a conductive oxide layer. Subsequent formation of a metallization layer on the device surface 87 and the passivation layer surface 89 can result in the unpassivated device side wall 83 being coated with the metallization material causing an interlayer electrical short.
The transition between the passivation layer surface 89 and the device surface 87 must be within an acceptable step height 90. In many cases, the acceptable step height 90 is defined, for a multi-layer semiconductor device 82, to be somewhat smaller than the thickness of the top layer defining the device surface 87 in order to prevent shorting between the adjacent device layer.
In some instances, the passivation layer 86 will contain micro defects (not shown), such as gas bubbles or voids. As the passivation layer 86 is etched back, any exposed voids will grow, possibly extending from the passivation layer surface 89 to the device side wall 83. This can also cause interlayer electrical shorting.
In some instances, a residue layer 84 of passivation material remains on the device surface 87 after the etching of the passivation layer 86. This residue layer 84 can remain for a number of reasons, such as, but not limited to, particle contamination masking the removal of the passivation layer 86, and carbonized passivation material caused by etching processes that is resistant to etch removal, among others. This residue layer 84 is detrimental to the quality of the interconnection between the device surface 87 and other devices.
The above passivation and planarization issues are compounded for complex integrated devices that have multiple devices having surfaces at different elevations above the substrate. This can be the result of varying process control in the growth or etch process used to produce the devices, such as to impart a desired functionality by adding to or etching from one or more devices. The surface of the integrated device must be quasi-planarized; that is, the integrated device surface will comprise multiple localized planarized surfaces corresponding to the multiple device elevations. In one fabrication technique, the devices are passivated and planarized at each common elevation in turn, from lowest to highest elevation, requiring a number of processing steps for each device elevation. This process is complex, time consuming, and has the potential for increased defect rates.
New methods are needed for the passivation and quasi-planarization of integrated devices having multiple device surfaces at multiple elevations above the substrate. The methods would preferably provide a small to zero step height, be relatively insensitive to passivation layer non-uniformity and etch non-uniformity, provide acceptable passivation of the device side wall, provide protection for the device against etch-induced damage, ensure a residue-free device surface, and/or prevent the detrimental effects of passivation layer voids. The methods preferably also have a low defect rate, impart little to no harm to the underlying desired material layers, and/or be reasonably economical.